[local_async_enable]
246 /* 247 * Unmask asynchronous aborts after bringing up possible earlycon. 248 * (Report possible System Errors once we can report this occurred) 249 */ 250 local_async_enable();
local_async_enable 的code 在 arch/arm64/include/asm/irqflags.h#L59
59 #define local_async_enable() asm("msr daifclr, #4" : : : "memory") 60 #define local_async_disable() asm("msr daifset, #4" : : : "memory")
對於SPSR 等system register只能透過msr or mrs 來存取
而 這些register中某些特定的欄位可以直接指定要 set 還是 clear
• MSR DAIFClr, #imm4 : clear any or all of DAIF to 1
• MSR DAIFSet, #imm4 : set any or all of DAIF to 0
• MSR SPSel, #imm4 : select stack pointer between EL0 to ELn
DAIF指得就是如下圖SPSR中的DAIF 四個field
• MSR SPSel, #imm4 : select stack pointer between EL0 to ELn
DAIF指得就是如下圖SPSR中的DAIF 四個field
According to ARM Programmers Guide for ARMv8
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D: Process state Debug mask. Indicates whether debug exceptions from watchpoint,
breakpoint, and software step debug events that are targeted at the Exception level
the exception occurred in were masked or not
若mask, 代表發生exception時core會知道
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A: SError (System Error) mask bit.
若mask, 代表發生system error時, core 會知道
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I: IRQ mask bit.
若mask, 代表IRQ不會被core 知道(IRQ不會打進來)
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F: FIQ mask bit.
若mask, 代表FIQ不會被core 知道(FIQ不會打進來)
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[History]
這一篇mailing list [3]說明了為什麼要加這個function
subject
[arm64: Unmask asynchronous aborts when in kernel mode]
The asynchronous aborts are generally fatal for the kernel but they can be masked via the pstate A bit. If a system error happens while in kernel mode, it won't be visible until returning to user space. This patch enables this kind of abort early to help identifying the cause.
作者提到當系統在kernel mode發生error時, 必須要等到return 到user space才會被看見
因此為了讓 abort 提早被發現, 他在 setup.c的setup_arch() 與 smp.c 的 secondary_start_kernel()中加入這個patch, 將可以看到system error的bit enable起來
[Asynchronous\Synchronous Exception]
個別說明兩種exception的差別
An exception is described as synchronous if it is generated as a result of execution or attempted execution of the instruction stream, and where the return address provides details of the instruction that caused it.- Instruction aborts from the MMU. For example, by reading an instruction from a memory location marked as Execute Never.
- Data Aborts from the MMU. For example, Permission failure or alignment checking.
- SP and PC alignment checking.
- Synchronous external aborts. For example, an abort when reading translation table.
- Unallocated instructions.
- Debug exceptions.
非同步例外: 是由 IRQ (normal priority interrupt), FIQ (fast interrupt) or SError (System Error)所引起. For example, an abort triggered by writeback of dirty data from a cache line to external memory
1. http://www.voidcn.com/blog/longwang155069/article/p-6147749.html
2. http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.den0024a/CHDDJBAB.html
3. http://marc.info/?l=git-commits-head&m=138574902028026&w=2